About TylSemi, Inc.
The Opportunity
The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?
That's what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.
This isn't a nice-to-have. It's the critical path.
Why NowThe Market Window
The semiconductor industry is going through its biggest architectural shift in 40 years:
• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.
Culture & Team: How We WorkNo Politics, No Bureaucracy
There are no layers, no approval chains, no corporate theater.
• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.
Remote-Friendly, Global Team
• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world-class design center in Bangalore
Move Fast, Ship Real Products
We're not a research project. We have paying customers, committed capital, and aggressive timelines.
This is a company, not a lifestyle business. We're building to win.
What We Value
• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.
The Ask
If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.
We're asking you to walk away from that and bet on us.
Here's why you should:
• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.
This is the bet. Join us and build something that matters.
Or stay comfortable. No judgment.
But if you're the kind of person who wants to take the shot, we'd love to talk.
READY TO JOIN?
Role Overview
We are seeking a highly skilled Staff Engineer – Physical Verification (PV) to lead physical verification and signoff activities for complex ASIC/SOC designs across advanced technology nodes. The ideal candidate will drive DRC, LVS, ERC, ANTENNA, and reliability verification closure while collaborating closely with Physical Design, Layout, Foundry, and CAD teams to enable high-quality and timely tape-outs. This role requires deep expertise in signoff methodologies, debugging complex violations, and driving automation and process improvements.
WhatYou’llDo
Lead block-level and full-chip physical verification and signoff activities for advanced SOC designs. Drive DRC, LVS, ERC, ANTENNA, density, and reliability closure using industry-standard signoff methodologies. Debug and resolve complex physical verification issues in collaboration with Physical Design, Custom Layout, and Foundry teams. Develop and maintain scalable PV automation flows, rule decks, and regression infrastructure. Analyze and resolve manufacturing and reliability challenges including EM/IR, latch-up, and ESD-related issues. Support hierarchical verification, tape-out execution, and final GDS signoff deliverables. Collaborate with CAD and EDA vendors for tool qualification, flow enhancement, and issue resolution. Mentor junior engineers and contribute to methodology development and best practices.
WhatWe’reLooking For
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field. 10+ years of experience in physical verification and signoff for ASIC/SOC designs. Strong expertise in DRC, LVS, ERC, ANTENNA, density checks, and debugging methodologies. Hands-on experience with industry-standard tools such as Calibre, ICV, Pegasus, or equivalent verification platforms. Good understanding of physical design flow, layout concepts, process technologies, and manufacturing requirements. Experience with advanced technology nodes including 7nm/5nm/3nm designs. Strong scripting and automation skills using Tcl, Python, Perl, or Shell. Excellent analytical, debugging, communication, and technical leadership skills.
Good to Have
Experience with reliability verification including EMIR, ESD, and latch-up analysis. Exposure to chiplet-based designs, 3D ICs, and advanced packaging technologies. Knowledge of foundry tape-out processes and signoff qualification requirements.
Success in This Role Looks Like
Successful closure of physical verification signoff for complex SOC tape-outs with high quality. Fast and efficient resolution of physical verification and manufacturing violations. Improved PV methodology scalability, automation, and execution efficiency. Strong technical leadership and mentoring contributions across engineering teams.
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