About Us:At InspireSemi, we're not just building chips; we're revolutionizing high-performance computing. Our groundbreaking architecture packs thousands of 64-bit CPU cores onto a single chip, all seamlessly connected. We're driven by a mission to make high performance computing more accessible, energy-efficient, and easier for developers to harness. Ready to make a real impact? Join our passionate team!
Why Join InspireSemi?- Be a Pioneer: Get in on the ground floor of a hypergrowth startup! You'll be part of a small, dynamic team shaping the future of computing.
- Make an Impact: Your work will directly contribute to disruptive technology.
- Grow With Us: Seize significant growth and development opportunities.
- Rewarding Compensation: We offer a competitive salary, bonus potential, and meaningful equity.
- Flexibility: Benefit from a hybrid work model (with potential for fully remote for exceptional candidates) and flexible time off.
The Opportunity:We are seeking a highly skilled and experienced Design for Test (DFT) engineer to join our team. The ideal candidate will have over 5 years of experience in end-to-end DFT flows, including RTL integration, scan insertion, ATPG pattern generation, and post-silicon diagnosis.
What You'll Do:- RTL and IP Integration: Generate RTL and integrate features like scan compression, SSN, and third-party IPs into designs.
- DFT Architecture & Implementation: Scan insertion, compression, boundary scan, IEEE 1149.1/1500/1687
- ATPG and Coverage: Generate ATPG scan compressed patterns and drive coverage closure for complex partitions using various fault models, including stuck-at, transition, cell-aware, and interconnect bridge/open.
- Timing and GLS: Generate timing constraints for backend teams for various scan modes. Run, debug, and sign off on partition and retargeting level GLS runs.
- UPF and Power Management: Analyze and fix UPF integration issues, working with front-end teams and EDA tool vendors. Develop and validate UPF for chips using EDA tools and simulations.
- Verification & Debug: PerformRTL/gate-level simulations, coverage analysis, ATE pattern bring-up.
- Post-Processing and Debug: Develop scripts and ECO flows for post-processing the design to address critical issues before tape-out. Debug simulation mismatches and silicon bring-up issues by running scan tests.
What You Bring:- 5+ years of experience in end-to-end DFT flows
- A Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering or related field.
- Proficiency in Tcl, Perl, Bash/Tcsh, Python, and Makefile.
- Experience with Cadence Incisiv/Xcelium (or equivalent tools).
- Strong understanding of Verilog, UPF, CPF, and BSDL.
- Extensive experience with Cadence Modus, Genus, Conformal and Xcelium tools (or Synopsys/Siemens equivalent - DFT Compiler, TetraMax, Tessent Fastscan, TestKompress, DFTAdvisor).
- Excellent communication and collaboration skills to work effectively with various teams and EDA tool vendors.
Bonus Points: - Experience in RISC-V architecture
- Large CPU based systems
- Experience on ADVANTEST 93K or equivalent ATE’s
If you're excited about pushing the boundaries of computing and working on truly innovative technology in a rewarding environment, we'd love to hear from you!
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